Memory cells of dynamic random access memories (DRAMs) comprise a storage capacitor for storing an electrical charge that characterizes an information content of the memory cell, and a selection transistor for addressing the storage capacitor. The selection transistor is formed as a field effect transistor in a semiconductor substrate. For the channel length of the selection transistor, a lower limit arises below which the insulation properties of the selection transistor in the turned-off state, corresponding to the nonaddressed state of the memory cell, are inadequate. The lower limit of the effective channel length Leff limits the scalability of planar transistor cells (PTC) with a selection transistor formed horizontally with respect to a substrate surface of the semiconductor substrate.
Cell arrangements with vertical transistor cells (VTC) have been described for memory cell arrangements having trench capacitors as storage capacitors. In this case, the source/drain regions of the selection transistor, in the semiconductor substrate, are oriented essentially vertically with respect to the substrate surface and are formed one above the other between the substrate surface and an upper edge of the trench capacitor embodied in the depth of the semiconductor substrate. In the addressed state of the memory cell, a channel controlled by a gate electrode of the selection transistor is formed between the two source/drain regions perpendicularly to the substrate surface. The channel width Weff arises in a manner dependent on the smallest feature size F that can be produced by means of a lithographic patterning method. The channel length Leff is dependent on the depth in which the lower source/drain region or a lower edge of the gate electrode is formed.
Disadvantages of such vertical transistor cells are the complicated integration thereof in memory cells with stacked capacitors and also, in the case of integration in memory cells with trench capacitors, the increase in the aspect ratio of a hole trench for the formation of trench capacitor and vertical transistor cell. What are furthermore disadvantageous are the parasitic action of the gate electrode of one selection transistor on the selection transistors adjacent to the selection transistor and also the switch-on/off current Ion that is limited in magnitude.
In other vertical memory cells with a vertical transistor structure, a body region formed between the two source/drain regions is completely surrounded by the gate electrode (surrounded gate vertical transistor cell, SGT). The first source/drain region of the selection transistor is formed in the base region of a semiconductor fin. A second source/drain region is provided at the upper edge of the semiconductor fin. The gate electrode extends along the four side walls of the semiconductor fin. The effective channel length Leff of such a vertical transistor structure results from the height of the semiconductor fin. The effective channel width Weff corresponds to the contour of the fin, at least one side length of the semiconductor fin arising in a manner dependent on the minimum feature size F. The total effective channel width correspondingly amounts to 2 F to 3 F. The integration of surrounded gate transistor cells in memory cells with stacked capacitors is complicated. In the case of integration in memory cells with trench capacitors, the high aspect ratios established in the course of processing at the hole trench and also the resultant restrictions with regard to the processing are disadvantageous.
In the case of recess channel field effect transistors (recess channel array transistor) the two source/drain regions are arranged in a horizontal plane with respect to the substrate surface. The gate electrode is provided in a recess trench introduced into the semiconductor substrate between the two source/drain regions of the field effect transistor. The effective channel length Leff results from the distance between the two source/drain regions and also the depth to which the recess trench is introduced into the semiconductor substrate. The effective channel width Weff corresponds to the minimum feature size F.
The switch-on/off current Ion/off is disadvantageously limited by the still restricted effective channel width. The integration of recess channel FETs in memory cell arrangements with a high memory cell density is made more difficult by the required alignment of the gate electrodes with respect to the recess trenches, for instance if the gate electrodes and the recess trenches are in each case patterned in the course of a dedicated photolithographic method step. In contrast to FinFETs or SGT transistor cells, the active zone is not shielded from adjacent memory cells by the gate electrode, so that a parasitic punchthrough of the potential of a gate electrode of one transistor structure to the transistor structures adjacent to said one transistor structure disadvantageously occurs.
An arrangement for memory cells having trench capacitors and selection transistors with a gate electrode recessed into the semiconductor substrate is described in U.S. Pat. No. 5,945,707.
In order to form fin field effect transistors (FinFETs), a semiconductor fin is formed in each case between two source/drain regions—formed horizontally with respect to the wafer surface—in the semiconductor substrate. A gate electrode structure adjoining the semiconductor fin on three sides is provided transversely with respect to the semiconductor fin. The effective channel length Leff of the fin field effect transistor is determined by the length of that section of the semiconductor fin which is enveloped by the gate electrode, in accordance with the minimum feature size F. The effective channel width Weff is determined from the height of the semiconductor fin, or the depth to which the semiconductor substrate is pulled back between the two source/drain regions on both sides of the semiconductor fin.
German patent application DE10361695.0, incorporated herein by reference, describes a curved channel field effect transistor (curved FET, CFET). The CFET is formed in a semiconductor fin formed from the semiconductor substrate. The two source/drain regions of the CFET are formed as doped zones at mutually opposite ends of the semiconductor fin and adjoining a substrate surface of the semiconductor substrate. Between the two source/drain regions, the semiconductor fin is recessed by means of a groove etching, whereby the channel length of the CFET results in accordance with the channel length of a recess channel FET. The gate electrode extends, in a manner insulated from the semiconductor fin by a gate dielectric, in sections along at least one of the longitudinal sides of the semiconductor fin. In accordance with the method for fabricating a memory cell arrangement having CFETs as selection transistors that is described in the above application, the semiconductor fins are arranged one after the other in the longitudinal direction to form cell rows in a manner electrically insulated from one another in each case. The gate electrodes of CFETs arranged in regard to a cell row are in each case sections of buried word lines that are provided in word line trenches running below the substrate surface along the semiconductor fins. In this case, the word lines are embedded in dielectric material that fills the word line trenches.
In memory cell arrangements having CFETs with gate electrode sections arranged on both sides of the semiconductor fin, a strand of two differently driven word lines is in each case situated opposite each other in the same word line trench. A high memory cell density leads to a high parasitic coupling capacitance between the word line strands running within the same word line trench.